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| MC642 PWM Fan Speed Controller with Fault Detection The MC642 is a pulse width modulation (PWM) fan speed controller for use with DC motors. It provides temperature proportional speed control. A thermistor connected to the VIN input furnishes the required control voltage of 1.25V to 2.65V for 0% to 100% PWM duty cycle. Minimum fan speed is set by a simple resistor divider on the VMIN input. An integrated Start-Up Timer ensures reliable motor start-up at turn-on, coming out of Shutdown Mode, or following a transient fault. A stalled, open, or unconnected fan causes the MC642 to trigger its start-up timer once. If the fault persists, the FAULT output goes low, and the device is latched in Shutdown Mode. Features * Shutdown Mode for Power Saving * Supports Low Cost NTC/PTC Thermistors * Temperature Proportional Speed for Acoustic Control / Longer Fan Life * Fan Voltage Independent of MC642 Supply Voltage * Fault Detection Circuits Protect Against Fan Failure and Aid System Testing * Operating Temperature Range: 0C to +85C http://onsemi.com SO-8 D SUFFIX CASE TBD PRELIMINARY INFORMATION * Power Supplies * Personal Computers * UPS's, Power Amplifiers, etc. TYPICAL APPLICATION DIAGRAM VDD Typical Applications 8-Pin DIP P SUFFIX CASE TBD PRELIMINARY INFORMATION PIN CONFIGURATION VIN 1 8 VDD CF 2 MC642D 7 VOUT VMIN 3 MC642P 6 FAULT +12 V D1 +5 V From Temp Sensor 1 Vin 8 VDD FAULT 6 1 0 Fault Detected RBASE Device 2 CF SENSE GND 4 5 MC642DR2 CSENSE RSENSE MC642P Q1 D2 GND 4 5 SENSE MC642 Reset FAN MC642 3 Vmin Vout 7 ORDERING INFORMATION Package 8-Pin SOIC 8-Pin Plastic DIP Shipping 2500 Tape/Reel 50 Tape/Reel + (Optional) (c) Semiconductor Components Industries, LLC, 1999 1 February, 2000 - Rev. 0 Publication Order Number: MC642/D MC642 FUNCTIONAL BLOCK DIAGRAM + - OTF SHDN - + CF 3 X TPWM Timer FAULT Start-Up Timer Missing Pulse Detector + - 70 mV (typ.) 10 kW Control Logic VOUT VDD VIN - + VOTF Clock Generator VMIN VSHDN + - MC642 GND SENSE PIN DESCRIPTION A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA 1 2 3 VIN CF The thermistor network (or other temperature sensor) connects to this input. A voltage range of 1.25V to 2.65V (typical) on this pin drives an active duty cycle of 0% to 100% on the VOUT pin. Positive terminal for the PWM ramp generator timing capacitor. The recommended CF is 1F for 30Hz PWM operation. VMIN An external resistor divider connected to this input sets the minimum fan speed by fixing the minimum PWM duty cycle (1.25V to 2.65V = 0% to 100%, typical). The MC642 enters Shutdown mode when 0 VMIN VSHDN. During Shutdown, the FAULT output is inactive, and supply current falls to 25A (typical). The MC642 exits Shutdown mode when VMIN VREL. See Applications section for more details. Ground Terminal 4 5 6 GND SENSE FAULT Pulses are detected at this pin as fan rotation chops the current through a sense resistor. The absence of pulses indicates a fault. Fault (open collector) output. This line goes low to indicate a fault condition. When FAULT goes low due to a fan fault, the device is latched in Shutdown Mode until deliberately cleared or until power is cycled. FAULT may be connected to VMIN if a hard shutdown is desired. FAULT will also be asserted when the PWM reaches 100% duty cycle, however the device will not latch itself off unless FAULT is tied to VMIN externally. PWM signal output. This active high complimentary output connects to the base of an external NPN motor drive transistor. This output has asymmetrical drive. - See Electrical Characteristics section. Power Supply Input. May be independent of fan power supply. See Electrical Characteristics section. 7 8 VOUT VDD Pin No. Symbol Description http://onsemi.com 2 MC642 ABSOLUTE MAXIMUM RATINGS* Parameter Package Power Dissipation (TA 70C) Plastic DIP Small Outline (SOIC) Derating Factors Supply Voltage Input Voltage, Any Pin Operating Temperature Range Maximum Chip Temperature Storage Temperature Range Lead Temperature (Soldering, 10 Seconds) * Maximum Ratings are those values beyond which damage to the device may occur. Value 730 470 8.0 6.0 (GND - 0.3) to (VCC + 0.3) 0 to +85 150 -65 to +150 +300 mW/C V V C C C C Unit mW ELECTRICAL CHARACTERISTICS (TMIN < TA < TMAX, VDD = 3.0V to 5.5V, unless otherwise noted.) Symbol VDD IDD IDD(SHDN) IIN VOUT Output tR tF t(SHDN) IOL IOH VIN, VMIN, Inputs VC(MAX), VOTF VC(SPAN) VSHDN VREL Input Voltage at VIN or VMIN for 100% PWM Duty Cycle VC(MAX) - VC(MIN) Voltage Applied to VMIN to Guarantee Shutdown Mode Voltage Applied to VMIN to Release Shutdown Mode VDD = 5V 2.5 1.3 -- VDD x 0.19 2.65 1.4 -- -- 2.8 1.5 VDD x 0.13 -- V V V V VOUT Rise Time (IOH = 5.0mA) (Note 1.) VOUT Fall Time (IOH = 1.0mA) (Note 1.) Pulse Width (On VMIN) to Clear Fault Mode VSHDN, VHYST Specifications Sink Current at VOUT Output VOL = 10% of VDD Source Current at VOUT Output VOH = 80% of VDD -- -- 30 1.0 5.0 -- -- -- -- -- 50 50 -- mA -- mA -- sec sec sec Supply Voltage Supply Current, Operating Pins 3, 5, 7 Open, CF = 1F, VIN = V(CMAX) Supply Current, Shutdown Mode Pins 1, 5, 6, 7 Open, CF = 1F, VIN = 0.35V (Note 1.) VIN, VMIN Input Leakage (Note 1.) Characteristic Min 3.0 -- -- -1.0 Typ -- 0.5 25 -- Max 5.5 1.0 A -- 1.0 A Unit V mA Pulse-Width Modulator F Sense Input VTH(SENSE) Fault Output VOL tMP tSTARTUP Output Low Voltage (IOH = 2.5mA) Missing Pulse Detector Timeout Startup Time -- -- -- -- -- 32/F 32/F 3/F 0.3 -- -- -- Hz Sec Sec Sec SENSE Input Threshold Voltage with Respect to GND 50 70 90 mV PWM Frequency (CF = 1.0F) 26 30 34 Hz tDIAG Diagnostic Timer Period 1. Guaranteed by design, not tested. http://onsemi.com 3 MC642 DETAILED OPERATING DESCRIPTION PWM The PWM (Pulse Width Modulation) circuit consists of a ramp generator and threshold detector. The frequency of the PWM is determined by the value of the capacitor connected to the CF input. A frequency of 30Hz is recommended (CF = 1F). The PWM is also the timebase for the startup and fault timer (see below). The PWM voltage control range is 1.25V to 2.65V (typical) for 0% to 100% output duty cycle. VOUT Output CAUTION: Shutdown mode is unconditional. i.e., the fan will not activate regardless of the voltage on VIN. (Note: The fan should not be shut down until all heat-producing activity in the system is at a negligible level.) SENSE Input The VOUT pin is designed to drive a low-cost transistor or MOSFET as the low side power switching element in the system. Various examples of driver circuits are shown in the following pages. This output has asymmetric complementary drive and is optimized for driving NPN transistors or N-channel MOSFET's. Since the system relies on PWM rather than linear power control, the dissipation in the power switch is kept to a minimum. Generally, very small devices (TO-92 or SOT package) will suffice. (See Output Drive Transistor Selection paragraph in Applications Information section.) Start-Up Timer The SENSE input, pin 5, is connected to a low-value current sensing resistor in the ground return leg of the fan circuit. During normal fan operation commutation occurs as each pole of the fan is energized. This commutation causes brief interruptions in the fan current, which is seen as pulses across the sense resistor. When the device is not in Shutdown Mode and pulses are not appearing at the SENSE input, a fault condition exists. The short, rapid changes in fan current (high dI/dt) cause corresponding dV/dt pulses across the sense resistor, RSENSE. The waveform on RSENSE is differentiated and converted to a logic-level pulse-train by CSENSE and the internal signal processing circuitry (See Figure 1). The presence and frequency of this pulse-train is a direct indication of fan operation. See the Applications Information section for more details. FAULT Output To ensure reliable fan startup, the StartUp Timer turns the VOUT output on for 32 cycles of the PWM whenever the fan is started from the off-state. This occurs at power-up and when coming out of shutdown mode. If the PWM frequency is 30Hz (CF = 1F), the resulting start-up time will be about one second. If a Fault is detected (see below), the Diagnostic Timer is triggered once, followed by the Startup-Up Timer. If the fault persists, the device is shut down. See FAULT Output below. Shutdown Control (Optional) When VMIN (pin 3) is pulled below VSHDN, the MC642 will go into Shutdown mode. This can be accomplished by driving VMIN with an open drain logic signal or using an external transistor as shown in Figure 1. All functions are suspended until the voltage on VMIN becomes higher than VREL (0.85V @ VDD = 5.0V). Pulling VMIN below VSHDN will always result in complete device shutdown and reset. The FAULT output is unconditionally inactive in Shutdown mode. A small amount of hysteresis, typically one percent of VDD (50mV at VDD = 5.0V), is designed into the VSHDN/VREL threshold. The levels specified for VSHDN and VREL in the Electrical Characteristics section include this hysteresis plus adequate margin to account for normal variations in the absolute value of the threshold and hysteresis. The MC642 detects faults in two ways: (1) Pulses appearing at SENSE due to the PWM turning on are blanked and the remaining pulses are filtered by a missing pulse detector. If consecutive pulses are not detected for 32 PWM cycles (1 Sec if CF = 1F), the Diagnostic Timer is activated and VOUT is driven continuously for three PWM cycles (100msec if CF = 1F). If a pulse is not detected within this window, the Startup-Timer is triggered. This should clear a transient fault condition. If the Missing Pulse Detector times out again, the PWM is stopped and FAULT goes low. When FAULT is activated due to this condition, the device is latched in Shutdown mode and will remain off indefinitely. (Diodes D1, D2 and resistor R5 (See Figure 1) are provided to ensure that fan restarting is the result of a fan fault, and not an over-temperature fault. A CMOS logic OR gate may be substituted for these components if available). When FAULT is activated due to this condition, the device is latched in Shutdown mode and will remain off indefinitely. Important: At this point, action must be taken to restart the fan by momentarily pulling VMIN below VSHDN, or by cycling system power. In either case the fan cannot be permitted to remain disabled due to a fault condition, as severe system damage could result. If the fan cannot be restarted, the system should be shut down. The MC642 may be configured to continuously attempt fan restarts if so desired. http://onsemi.com 4 MC642 VDD R5 10 k 0.1 mF +5 V 8 +5 V VDD From Vin FAULT 6 Temp 1 Sensor MC642 0.01 CB From System Shutdown Controller R1 R4 + (Optional) +12 V D1 D2 MC642 Reset 1 0 Fault Detected FAN Q1 RBASE R3 3 Vmin Vout 7 2 CF 1 mF CF SENSE GND 4 5 CSENSE RSENSE * The parallel combination of R3 and R4 must be > 10 k. Figure 1. Typical Fan Control Application Continuous restart mode is enabled by connecting the FAULT output to VMIN through a 0.1F capacitor as shown in Figure 1. When so connected, the MC642 automatically attempts to restart the fan whenever a fault condition occurs. When the fault output is driven low, the VMIN input is momentarily pulled below VSHDN, initiating a reset and clearing the fault condition. Normal fan startup is then attempted as previously described. The FAULT output may be connected to external logic (or the interrupt input of a microcontroller) to shut down the MC642 if multiple fault pulses are detected at approximately one second intervals. (2) FAULT is also asserted when the PWM control voltage applied to VIN becomes greater than that needed to drive 100% duty cycle (see Electrical Characteristics). This indicates that the fan is at maximum drive and the potential exists for system overheating. Either heat dissipation in the system has gone beyond the cooling system's design limits or some other fault exists such as fan bearing failure or an airflow obstruction. This output may be treated as a System Overheat warning and used to trigger system shutdown. However in this case, the fan will continue to run even when FAULT is asserted. If a shutdown is desired, FAULT may be connected to VMIN outside the device. This will latch the MC642 in Shutdown Mode when any fault occurs. SYSTEM BEHAVIOR The flowcharts describing the MC642's behavioral algorithm are shown in Figure 3. They can be summarized as follows: Power-Up (1) Assuming the device is not being held in Shutdown mode (VMIN > VREL): (2) Turn VOUT output on for 32 cycles of the PWM clock. This ensures that the fan will start from a dead stop. (3) During this Start-up time, if a fan pulse is detected then branch to Normal Operation; if none are received. (4) Activate the 32-cycle Start-up Timer one more time and look for fan pulses; if a fan pulse is detected, proceed to Normal Operation; if none are received.... (5) Proceed to Fan Fault (6) End After this period elapses, the MC642 begins normal operation. http://onsemi.com 5 MC642 +5 V* R1 NTC 1 mF CB +12 V R2 0.01 CB FAN 8 VDD 1 Vin FAULT 6 Thermal Shutdown RBASE Vout 7 Q1 R3 0.01 CB Shutdown (Optional) MC642 3 Vmin R4 + 2 CF 1 mF CF SENSE GND 4 5 CSENSE RSENSE NOTE: *See Cautions Regarding Latch-Up Considerations in the Applications Section. Figure 2. Typical Fan Control Application using NTC thermistor Normal Operation Normal Operation is an endless loop which may only be exited by entering Shutdown mode or Fan Fault. The loop can be thought of as executing at the frequency of the oscillator and PWM. (1) Reset the Missing Pulse Detector (2) Is MC642 in Shutdown? If so... a. VOUT duty-cycle goes to zero. b. FAULT is disabled. c. Exit the loop and wait for VMIN > VREL to resume operation (indistinguishable from Power-Up). (3) If an over-temperature fault occurs (VIN > VOTF) then activate FAULT; release FAULT when VIN < VOTF. (4) Drive VOUT to a duty-cycle porportional to greater of VIN and VMIN on a cycle by cycle basis. (5) If a fan pulse is detected, branch back to the start of the loop. (6) If the missing pulse detector times out ... (7) Activate the 3-cycle Diagnostic Timer and look for pulses; if a fan pulse is detected, branch back to the start of the loop; if none are received... (8) Activate the 32-cycle Startup Timer and look for pulses; if a fan pulse is detected, branch back to the start of the loop; if none are received... (9) Quit Normal Operation and go to Fan Fault. (10) End Fan Fault Fan Fault is essentially an infinite loop wherein the MC642 is latched in Shutdown Mode. This mode can only be released by a Reset, i.e., VMIN being brought below VSDHN, then above VREL, or by power-cycling. (1) While in this state, FAULT is latched on (low), and the VOUT output is disabled. (2) A Reset sequence applied to the VMIN pin will exit the loop to Power Up. (3) End http://onsemi.com 6 MC642 Normal Operation Power-Up Power-On Reset FAULT = 1 Clear Missing Pulse Detector YES VIN < VSHDN NO NO VIN > VREL? Initiate Start- Up Timer (1 Sec) YES YES Power-Up Fan Pulse Detected? YES YES Fan Pulse Detected? NO Fan Fault YES Fan Pulse Detected? NO NO Initiate Start- Up Timer (1 Sec) YES VIN > VOTF? NO VOUT Proportional To Greater of VIN or VMIN FAULT = 0 Shutdown VOUT = 0 VIN < VSHDN? NO VIN > VREL YES Shutdown VOUT = 0 NO Normal Operation Fan Fault NO M.P.D. Expired? YES FAULT = Low, VOUT Disabled YES Initiate Diagnostic Timer (100 mSec) NO VIN < VSHDN? YES NO Cycling Power? NO Fan Pulse Detected? Initiate Start- Up Timer (1 Sec) YES YES NO Fan Pulse Detected? NO Fan Fault VIN > VREL? YES Power-Up Figure 3. MC642 Behavioral Algorithm Flowchart http://onsemi.com 7 MC642 APPLICATIONS INFORMATION Designing with the MC642 involves the following: (1) The temp sensor network must be configured to deliver 1.25V to 2.65V on VIN for 0% to 100% of the temperature range to be regulated. (2) The minimum fan speed (VMIN) must be set. (3) The output drive transistor and associated circuitry must be selected. (4) The Sense Network, RSENSE and CSENSE, must be designed for maximum efficiency while delivering adequate signal amplitude. VDD IDIV (5) If Shutdown capability is desired, the drive requirements of the external signal or circuit must be considered. Temperature Sensor Design The temperature signal connected to VIN must output a voltage in the range of 1.25V to 2.65V (typical) for 0% to 100% of the temperature range of interest. The circuit of Figure 4 is a convenient way to provide this signal. VDD T1 R1 R1 IIN Vin R2 IDIV VMIN R2 GND Figure 4. Temperature Sensing Circuit Figure 5. VMIN Circuit VDD VDD FAN FAN RBASE VOH = 80% VDD +VR(BASE)- +VBE(SAT)- + VR(SENSE) - Q1 VOUT SENSE RSENSE RBASE Q1 CSENSE (0.1 mF Typ.) RSENSE GND GND Figure 6. Circuit for Determining RBASE Figure 7. SENSE Network http://onsemi.com 8 MC642 Figure 4 illustrates a simple temperature dependent voltage divider circuit. T1 is a conventional NTC thermistor, and R1 and R2 are standard resistors. The supply voltage, VDD, is divided between R2 and the parallel combination of T1 and R1. (For convenience, the parallel combination of T1 and R1 will be referred to as RTEMP.) The resistance of the thermistor at various temperatures is obtained from the manufacturer's specifications. Thermistors are often referred to in terms of their resistance at 25C. A thermistor with a 25C resistance on the order of 100kW will result in reasonable values for R1, R2, and IDIV. In order to determine R1 and R2, we must specify the fan duty-cycle, i.e. VIN, at any two temperatures. Equipped with these two points on the system's operating curve and the thermistor data, we can write the defining equations: VDD x R2 = V(t1) RTEMP (t1) + R2 VDD x R2 = V(t2) RTEMP (t2) + R2 IDIV = 1e-4A = R1 + R2 = 5.0V R1 + R2 , therefore (4.) 5.0V 1e-4A = 50,000W = 50kW We can further specify R1 and R2 by the condition that the divider voltage is equal to our desired VMIN. This yields the following equation: VMIN =VDD x R1 R1 + R2 (5.) Solving for the relationship between R1 and R2 results in the following equation: (1.) R1 = R2 x VDD - VMIN VMIN (6.) Where t1 and t2 are the chosen temperatures and RTEMP is the parallel combination of the thermistor and R1. These two equations permit solving for the two unknown variables, R1 and R2. Note that resistor R1 is not absolutely necessary, but it helps to linearize the response of the network. Minimum Fan Speed In the case of this example, R1 = (1.762) R2. Substituting this relationship back into Equation 4 yields the resistor values: R2 = 18.1kW, and R1 = 31.9kW A voltage divider on VMIN sets the minimum PWM duty cycle and, thus, the minimum fan speed. As with the VIN input, 1.25V to 2.65V corresponds to 0% to 100% duty cycle. Assuming that fan speed is linearly related to duty-cycle, the minimum speed voltage is given by the equation: VMIN = Minimum Speed x (1.4V) + 1.25V Full Speed (2.) For example, if 2500 RPM equates to 100% fan speed, and a minimum speed of 1000 RPM is desired, then the VMIN voltage is: VMIN = 1000 2500 x (1.4V) + 1.25V = 1.81V (3.) The VMIN voltage may be set using a simple resistor divider as shown in Figure 5. Per the Electrical Characteristics, the leakage current at the VMIN pin is no more than 1A. It would be very conservative to design for a divider current, IDIV, of 100A. If VDD = 5.0V then... In this case, the standard values of 32kW and 18kW are very close to the calculated values and would be more than adequate. One boundary condition which may impact the selection of the minimum fan speed is the irregular activation of the Diagnostic Timer due to the MC642 "missing" fan commutation pulses at low speeds. Typically, this only occurs at very low duty-cycles (25% or less). It is a natural consequence of low PWM duty-cycles. Recall that the SENSE function detects commutation of the fan as disturbances in the current through RSENSE. These can only occur when the fan is energized, i.e., VOUT is "on". At very low duty-cycles, the VOUT output is "off" most of the time. The fan may be rotating normally, but the commutation events are occuring during the PWM's off-time. The phase relationship between the fan's commutation and the PWM edges tends to "walk around" as the system operates. At certain points, the MC642 may fail to capture a pulse within the 32-cycle Missing Pulse Detector window. When this happens, the 3-cycle Diagnostic Timer will be activated, the VOUT output will be active continuously for three cycles and, if the fan is operating normally, a pulse will be detected. If all is well, the system will return to normal operation. There is no harm in this behavior, but it may be http://onsemi.com 9 MC642 audible to the user as the fan will accelerate briefly when the Diagnostic Timer fires. For this reason, it is recommended that VMIN be set no lower than 1.8V. SENSE Network (RSENSE and CSENSE) Table 1. RSENSE vs. Fan Current Nominal Fan Current (mA) 50 100 150 200 250 300 350 400 450 500 RSENSE (W) 9.1 4.7 3.0 2.4 2.0 1.8 1.5 1.3 1.2 1.0 The network comprised of RSENSE and CSENSE allow the MC642 to detect commutation of the fan motor. This network can be thought of as a differentiator and threshold detector. The function of RSENSE is to convert the fan current into a voltage. CSENSE serves to AC-couple this voltage signal and provide a ground-referenced input to the SENSE pin. Designing a proper SENSE Network is simply a matter of scaling RSENSE to provide the necessary amount of gain, i.e., the current-to-voltage conversion ratio. A 0.1F ceramic capacitor is recommended for CSENSE. Smaller values require larger sense resistors, and higher value capacitors are bulkier and more expensive. Using a 0.1F results in reasonable values for RSENSE. Figure 7 illustrates a typical SENSE Network. Figure 8 shows the waveforms observed using a typical SENSE Network. Table 1 lists the recommended values of RSENSE according to the nominal operating current of the fan. Note that the current draw specified by the fan manufacturer may not be the fan's nominal operating current, but may be a worst-case rating for near-stall conditions. The values in the table refer to actual average operating current. If the fan current falls between two of the values listed, use the higher resistor value. The end result of employing Table 1 is that the signal developed across the sense resistor is approximately 450mV in amplitude. Figure 8. SENSE Waveforms VDD VDD VDD FAN FAN FAN RBASE VOUT Q1 RBASE VOUT Q1 VOUT Q2 Q1 RSENSE RSENSE RSENSE GND a) Single Bipolar Transistor GND b) Darlington Transistor Pair GND c) N-Channel MOSFET Figure 9. Output Drive Transistor Circuit Topologies http://onsemi.com 10 MC642 Output Drive Transistor Selection The MC642 is designed to drive an external transistor for modulating power to the fan. This is shown as "Q1" in Figures 2, 6, 7, 9, 10, and 11. The VOUT pin has a minimum source current of 5mA and a minimum sink current of 1mA at VDD = 5.0V. Bipolar transistors or MOSFET's may be used as the power switching element as shown below. When high current gain is needed to drive larger fans, two transistors may be used in a Darlington configuration. These circuit topologies are shown in Figure 9: (a) shows a single NPN transistor used as the switching element; (b) Illustrates the Darlington pair; and (c) shows an N-channel MOSFET. One major advantage of the MC642's PWM control scheme versus linear speed control is that the dissipation in the pass element is kept very low. Generally, low-cost devices in very small packages such as TO-92 or SOT, can be used effectively. For fans with nominal operating currents of no more than 200mA, a single transistor usually suffices. Above 200mA, the Darlington or MOSFET solution is recommended. For the fan sensing function to work correctly it is imperative that the pass transistor be fully saturated when "on". The minimum gain (hFE) of the transistor in question must be adequate to fully saturate the transistor when passing the full fan current while being driven within the 5mA IOH of the VOUT output. Table 2 gives examples of some commonly available transistors. This table is a guide only. There are many transistor types which might work as well as those listed. The only critical issues when choosing a device to use as Q1 are: (1) the breakdown voltage, VCE(BR), must be large enough to stand off the highest voltage applied to the fan (NOTE: this may be when the fan is off!); (2) the gain (hFE) must be high enough for the device to remain fully saturated while conducting the maximum expected fan current and being driven with no more than 5mA of base/gate drive at maximum temperature; (3) rated fan current draw must be within the transistor's current handling capability; and (4) power dissipation must be kept within the limits of the chosen device. Table 2. Transistors for Q1 Device MPS2222 MPS2222A 2N4400 2N4401 MPS6601 MPS6602 VBE(SAT) 1.3 1.2 0.95 0.95 1.2 1.2 MIN hFE 100 100 50 100 50 50 VBR(CEO) 30 40 40 40 25 40 IC 150 150 150 150 500 500 RBASE (W) 800 800 820 820 780 780 A base-current limiting resistor is required with bipolar transistors. This is shown in Figure 6. The correct value for this resistor can be determined as follows: (see Figure 6). VOH = VSENSE + VBE(SAT) + VRBASE VRSENSE = IFAN X RSENSE (7.) VRBASE = RBASE X IBASE IBASE = IFAN / hFE VOH is specified as 80% of VDD in the Electrical Characteristics table; VBE(SAT) is given in the transistor datasheet. It is now possible to solve for RBASE. RBASE = VOH - VBE(SAT) - VRSENSE IRBASE (8.) Some applications require the fan to be powered from the negative 12V supply to keep motor noise out of the positive voltage power supplies. As shown in Figure 10, Zener diode D2 offsets the -12V power supply voltage holding transistor Q1 OFF when VOUT is LOW. When VOUT is HIGH, the voltage at the anode of D2 increases by VOH, causing Q1 to turn ON. Operation is otherwise the same as the case of fan operation +12V. Latch-up Considerations As with any CMOS IC, the potential exists for latch-up if signals are applied to the device which are outside the power supply range. This is of particular concern during power-up if the external circuitry, such as the sensor network, VMIN divider, shutdown circuit, or fan, are powered by a supply different from that of the MC642. Care should be taken to ensure that the MC642's VDD supply powers-up first. If possible, the networks attached to VIN and VMIN should connect to the VDD supply at the same physical location as the IC itself. Even if the IC and any external networks are powered by the same supply, physical separation of the connecting points can result in enough parasitic capacitance and/or inductance in the power supply connections to delay one power supply "routing" versus another. Power Supply Routing and Bypassing Noise present on the VIN and VMIN inputs may cause erroneous operation of the FAULT output. As a result, these inputs should be bypassed with a 0.01F capacitor mounted as close to the package as possible. This is particularly true of VIN, which usually is driven from a high impedance source (such as a thermistor). In addition, the VDD input should be bypassed with a 1F capacitor. Grounds should be kept as short as possible. To keep fan noise off the MC642 ground pin, individual ground returns for the MC642 and the low side of the fan current sense resistor should be used. http://onsemi.com 11 MC642 5V VDD FAN MC642 Vout D2 12 V Zener GND R2 2.2 k Q1 R4 10 k R3 2.2 W -12 V Figure 10. Powering Fan From -12V Supply Design Example (Figure 11) Step 1. Circulate R1 and R2 based on using an NTC having a resistance of 4.6kW at TMIN and 1.1kW at TMAX. R1 = 75kW R2 = 1kW Step 2. Set minimum fan speed VMIN = 1.8V +5 V +5 V NTC 10 kW @ 25C 0.01 mF CB +5 V 1 R5 33 k 0.01 CB Q2 (Optional) Limit the divider current to 100A from which R5 = 33k and R6 = 18kW Step 3. Design the output circuit Maximum fan motor current = 250mA. Q1 beta is chosen at 100 from which R7 = 1.5kW R1 + 1 mF CB +12 V R2 FAN 4 VCC GND Vin FAULT 6 System Fault R7 1.5 k Q1 8 MC642 3 Vmin Vout 7 R8 10 k Fan Shutdown R6 + 2 C1 1 mF CF SENSE 5 CSENSE 0.1 mF RSENSE 2.2 W Figure 11. Design Example http://onsemi.com 12 MC642 MC642 as a Microcontroller Peripheral (Figure 12) In a system containing a microcontroller or other host intelligence, the MC642 can be effectively managed as a CPU peripheral. Routine fan control functions can be performed by the MC642 without processor intervention. The micro-controller receives temperature data from one or more points throughout the system. It calculates a fan operating speed based on an algorithm specifically designed for the application at hand. The processor controls fan speed using complementary port bits I/01 through I/03. Resistors R1 through R6 (5% tolerance) form a crude 3-bit DAC that translates the 3-bit code from the processor's outputs into a 1.6V DC control signal. (A monolithic DAC or digital pot may be used instead of the circuit shown.) With VMIN set to 1.8V, the MC642 has a minimum operating speed of approximately 40% of full rated speed when the processor's output code is 000. Output codes 001 to 111 operate the fan from roughly 40% to 100% of full speed. An open drain output from the processor can be used to reset the MC642 following detection of a fault condition. The FAULT output can be connected to the processor's interrupt input, or to an I/O pin for polled operation. +5 V Open Drain Output +12 V (RESET) (Optional) I/O0 R1 (MSB) 110 k R2 240 k I/O2 R3 360 k I/O3 (LSB) R4 18 k R5 1.5 k + R7 33 k +5 V R6 1k R8 18 k 2 1 mF 3 CB 0.01 mF 4 Vmin FAULT 6 1 CB 0.01 mF +5 V Vin VDD 8C B MC642 1 mF Vout 7 +5 V R10 10 k + R9 1.5 k - 2N2222A + FAN Analog or Digital Temperature Data from One or More Sensors I/O1 CMOS Outputs CF CMOS +5 V Microcontroller GND SENSE 5 0.1 mF R11 2.2 W GND INT Figure 12. Design Example http://onsemi.com 13 MC642 PACKAGE DIMENSIONS 8-Pin DIP PLASTIC PACKAGE CASE TBD ISSUE TBD PIN 1 .260 (6.60) .240 (6.10) .045 (1.14) .030 (0.76) .070 (1.78) .045 (1.14) .310 (7.87) .290 (7.37) .400 (10.16) .348 (8.84) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .400 (10.16) .310 (7.87) 3 MIN. .110 (2.79) .090 (2.29) .022 (0.56) .015 (0.38) Dimensions: inches (mm) http://onsemi.com 14 MC642 PACKAGE DIMENSIONS 8-Pin SOIC PLASTIC PACKAGE CASE TBD ISSUE TBD PIN 1 indicated by dot and/or beveled edge .157 (3.99) .244 (6.20) .150 (3.81) .228 (5.79) .050 (1.27) TYP. .197 (5.00) .189 (4.80) .069 (1.75) .053 (1.35) .010 (0.25) .004 (0.10) 8 _ MAX. .050 (1.27) .016 (0.40) Dimensions: inches (mm) .010 (0.25) .007 (0.18) .018 (0.46) .014 (0.36) http://onsemi.com 15 MC642 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. 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